In many present day wireless communication applications, a digital synthesizer is used and often implemented by way of a digital phase locked loop (DPLL) that is used to control a digitally controlled oscillator (DCO) to generate (often referred to as ‘synthesize’) an output radio frequency (local oscillator) signal. Such digital synthesizers provide the benefit of simplifying the integration of the synthesizer circuitry within large scale integrated digital circuit devices, as compared with equivalent analogue synthesizers, thereby reducing size, cost, power consumption and design complexity. Furthermore, DPLLs intrinsically present lower phase noise than their analogue counterparts.
All-digital phase locked loops (ADPLLs) can be used as a frequency synthesizer in radio frequency circuits to create a stable local oscillator for transmitters or receivers, due to their low power consumption and high integration level. They can also be used to generate the frequency-modulated continuous wave (FMCW) waveforms required by a radar transmitter.
FIG. 1 illustrates a conventional digital phase locked loop (DPLL) 100. An N-bit digital FCW 105 is provided to a phase comparator 110, which compares an N-bit digital feedback signal 155 to the FCW 105, and outputs an N-bit oscillator control signal 115 based on the comparison of the digital feedback signal 155 to the FCW 105. A digital low pass filter 120 filters the N-bit oscillator control signal 115, and outputs a filtered N-bit oscillator control signal 125, which is provided to a digitally controlled oscillator (DCO) 130. For completeness, it is noted that a portion of the DCO may reside in the analog domain for radar applications that require very good phase noise. The DCO 130 outputs a frequency signal 135 based on the filtered N-bit oscillator control signal 125. A feedback path of the DPLL 100 consists of a divider 140 that divides the output frequency signal 135 to generate a frequency-divided signal 145, which is provided to a time-to-digital converter (TDC) 150. The TDC 150 also receives a reference frequency signal 165, which is used to sample the frequency-divided signal 145. The TDC 150 outputs the N-bit digital feedback signal 155 based on a measured time interval between the frequency-divided signal 145 and the reference frequency signal 165.
In ADPLLs, one of the key building blocks is the Time-to-Digital converter (TDC). The TDC circuit measures the oscillation period of the DCO using the reference frequency period as a reference. The most important parameters in the TDC circuit are its resolution, time dynamic range and linearity. In this context, the time resolution must be as low as possible, as it is the limiting factor to achieve very low in-band phase-noise levels that are required in high performance applications. The time-to-digital converter (TDC) must also be able to measure, with the above-mentioned low time resolution, a sufficiently long DCO period. Lastly, the TDC response, i.e. the output code versus the input time, must be linear.
Solutions exist that provide either a low resolution or a long DCO period, but not both at the same time. Accordingly, a need exists to provide a synthesizer circuit and a method to achieve both of these requirements.
Known ADPLLs have rarely been used in FMCW radar systems and devices, as yet, due to the extremely demanding phase-noise performances that are required in such systems and devices, and also very demanding level of spurious signals that are needed, which are extremely difficult to attain with an ADPLL. The known technique disclosed in CN 104320130 A describes a dual TDC circuit that includes one medium-resolution TDC circuit that uses a tapped delay-line (based on an inverter delay) and one fine-resolution TDC circuit that uses a Vernier delay-line. The proposed architecture in this document requires a significant amount of analog circuitry (namely three delay locked loops (DLLs), two phase-detectors plus charge-pumps and loop filters, an analog OR gate, replica delay, etc.) between the medium-resolution TDC circuit and the fine-resolution TDC circuit. Such a complex design is used to attempt a smooth handover from the medium to fine TDC, as well as to calibrate both TDC circuits. However, due to the handover from the medium TDC to the fine TDC operation the architecture fails to provide linearity of the generated signal in a long DCO period and a low resolution cannot be achieved. Furthermore, such a solution is both costly and die-consuming.
U.S. Pat. No. 7,932,847 B1 also describes a dual TDC circuit that includes one medium-resolution and one fine-resolution circuit that uses two delay-lines. This solution includes a complex analog circuit of a time-based amplifier between the medium-resolution TDC circuit and the fine-resolution TDC circuit in order to attempt a smooth handover from the medium to fine TDC. The time-based amplifier requires additional calibration. The use of complex analog circuitry may generate errors during the calibration, which yields a degradation of the fine-resolution performance. These known TDC architectures may also create linearity problems when jumping from medium TDC to a fine TDC.